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SuperSpread t1_j26oj3n wrote

This is the first actual futurology post I’ve seen on this sub through the front page in 2 months. Thank you.

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filosoful OP t1_j25jnm7 wrote

Taiwan Semiconductor Manufacturing Co. (TSMC), the world's largest contract chipmaker, touted its 3 nanometer process as the world's most advanced semiconductor technology on Thursday at a ceremony announcing the start of mass production of chips using the highly anticipated technology.

The 3nm process yield rate is comparable to that of the 5nm technology and demand for 3nm chips is very strong, said TSMC Chairman Mark Liu (劉德音) during the ceremony held at TSMC's Fab 18 in the Southern Taiwan Science Park in Tainan.

Liu said TSMC's 3nm technology would feature an estimated 60 percent gain in density of logic transistors and reduce power consumption by 30 percent to 35 percent at the same rate compared with 5nm technology.

Higher logic density means smaller transistors that operate faster and require less power to operate can be produced.

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FlatulentWallaby t1_j25qdiw wrote

Is there a theoretical minimum size they can reach?

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Boring_Ad_3065 t1_j25tnfz wrote

Yes, and they’ve been consistently pushing up against it. The smallest features on these chips are literally atoms wide and at a point where electrons can jump across them, requiring very creative materials and use of more 3d-like layers. Getting “light” wavelengths small enough is also an issue and it took a long time to get the last upgrade working.

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HashedEgg t1_j261dq1 wrote

Transistor size of 3nm is getting to the size of what? 12ish silicon atoms? Most mindblowing thing are those x ray lazer thingy machines ASML makes to make those chips with. Pure sifi machinery.

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r2k-in-the-vortex t1_j265wfw wrote

Silicon crystal structure is like so, therefore 3nm is 5.5 repeating units long. There is no feature this small in a transistor. I don't know the figures for TSMC 3nm, but for 5nm Samsung 5LLP process the fin pitch is 27nm. That's the smallest dimension in the transistor. How it translates to 5nm is a matter of history and marketing.

With plain old planar process it was a straightforward matter, make the transistor smaller you make it faster and more energy efficient. So that's where using the nanometers came from. That ran up against the wall at about 32nm. The next innovation from that was finfets, which is a different way to construct a transistor and make it more energy efficient and faster.

But it's still the same size, how are you going to sell it to consumer than is used to buying nanometers? You fib it a little and say, if with planar technology we made a transistor 14nm size, then it would be as fast and energy efficient as this transistor right here. And that's what the nanometers are these days, they are not actual dimensions anymore.

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HashedEgg t1_j2673iq wrote

Aaah that makes waaay more sense, thanks! So basically all the terminology bs we have in computer hardware goes down to component level... Marketing terms can be so annoying...

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r2k-in-the-vortex t1_j26a30w wrote

Just wait until you learn about camera sensors.

Reality is that customer buys a functionality and really only very superficially cares about how things are built or why they are built a certain way. That's how you get these sorts of pseudo specs that are really just marketing terms.

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paint-roller t1_j26q4ss wrote

Unless using cameras is your job no one other than the engineers who make or services cameras/sensors/lenses needs to know this stuff....actually I doubt most people who operate cameras for a living know that 2/3, 1/2, 1/3 inch sensors get their classification based off of old imaging tunes.

It is pretty interesting though.

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SaintsNoah t1_j27j9yz wrote

Thank you for explaining this. I've read many times that "the numbers dont mean anything" but the way you explain it is far from arbitrary. Sounds like the concept of measuring cars in Horsepower

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r2k-in-the-vortex t1_j282a2w wrote

Pretty much, it's a comparison to legacy that has lost it's meaning.

The only comparison that really matters is functional comparison to one generation before - "Liu said TSMC's 3nm technology would feature an estimated 60 percent gain in density of logic transistors and reduce power consumption by 30 percent to 35 percent at the same rate compared with 5nm technology."

That's real deal. But the 5nm and 3nm classification, that's marketing term that has lost it's meaning.

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Auberginebabaganoush t1_j2746xp wrote

So. To be clear. The smallest actually measurable component is around 27 nm, and saying 3 or 5nm is just saying that this is the equivalent efficiency of a planar transistor?

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TerpenesByMS t1_j29v5sm wrote

So it IS a fib based in marketing! Thank you for the enlightenment!

This makes sense, with the marketing being "equivalent to theoretical planar transistors of X nm".

So, if I infer correctly, tunneling is still a technical wall of sorts, and the game is more about optimizing actual logic gate and circuit design more than simply shrinking components like it used to be?

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r2k-in-the-vortex t1_j2b143d wrote

Yeah, finfets and ongoing transition to gate all around fets is basically more efficient, but geometrically more complicated ways to build a transistor.

Don't get me wrong, the components are still shrinking, EUV rollout has been a gamechanger for that. But that shrinking doesn't keep pace with nanometer node numbers anymore because modern transistors are just not the same as planar process transistors were.

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miguelandre t1_j27mawu wrote

My buddy works for them (ASML) and is heading back to the Netherlands for a year to become a “machine father” again. Cool shit.

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HashedEgg t1_j2agfbh wrote

A friend of mine applied for them too, so they might become collegues

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r2k-in-the-vortex t1_j263cmz wrote

Yes, you can't go smaller than the lattice constant or the material doesn't behave as crystal anymore.

But size isn't really the limitation and there is really no feature about these transistors that is 3nm long. The real kicker is power efficiency.

>reduce power consumption by 30 percent to 35 percent

Power use is the limit. There is obvious supply limit for portables etc. But for all chips, the limit is that you need to cool it and you have to keep it at pretty low temperatures even while it's consuming a lot of power. That means the vent noise goes straight up and that's a deal breaker for home users. In server rooms the noise is less of a problem, but you can still only dump so much power in a little chip before you are unable to carry away the heat.

In practice power use and cooling are what dictate how much computation you can actually do with a chip, so if you want to do more you need more power efficient transistors that don't heat up as much for any given computation.

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Riegel_Haribo t1_j28j6jl wrote

When they can't reach it, they just make up a number. That's how their process naming has worked for a while.

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Sidewaysouroboros t1_j28bi8c wrote

And this right here is why big daddy USA will come to save them from China when needed.

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Hisako1337 t1_j27xl26 wrote

Electronic circuits are reaching physical limits here. The next step (still in its infancy but getting there) will be optical circuits.

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DisturbedNeo t1_j2a21l0 wrote

For the people wondering “What’s the limit” or “What happens at 1nm”, you should know that “3nm” is just marketing speak, not the real size of the die. It doesn’t mean anything, other than it’s better than “4nm”.

According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.

That said, after “3nm” they’ll go to “2nm”, and after that they’ll start referring to things in “Angstrom” terms instead. 20A, 18A, and so on.

1A = 0.1nm

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PHA_TE t1_j28stit wrote

We are at the point where printed material circuitry will start coming down to consumers in the next decade. This is the final hardware leap before we hit a wall. After that we are making gains through software and protocol optimization. (As an engineer, really nothing dramatic has changed in computing hardware since the 60s.)

I’m more excited about democratizing of programming via use of ai. We will see a dramatic drop in cost, and increase in quality when your average consumer can “write their own programs.”

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routerg0d t1_j29ebzz wrote

Problem is at around 10nm chips quit getting more efficient power wise. Below that the amount of power to drive the chip began rising quickly. A 3nm chip will need more power than a 5nm chip. Apple saw this and moved to RISC based chips because RISC requires less power on the same sized chip process.

GPUs are really hitting a wall because of this as well.

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vorpal_potato t1_j2erw46 wrote

TSMC is claiming that their 3nm process uses 20-30% less power than a comparable chip made with their 5 nm process, and they've got a version bump in progress which they say will use only half as much power as a 5 nm chip with equal performance. Pretty consistently the sub-10nm processes have delivered better power efficiency in practice, which is the opposite of what you said. (Maybe you meant to make some more nuanced point about e.g. dynamic current vs. leakage current?)

Also, that's not even remotely why Apple switched from Intel chips to their own. They switched because Apple had managed to beat Intel at microarchitecture, the way the chip works inside. The instruction set doesn't really make much difference except in the instruction decoding portion, which isn't that big a part of the chip these days. The RISC/CISC distinction used to be real, but now it's as outdated as falconry and fax machines.

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FuturologyBot t1_j25odlf wrote

The following submission statement was provided by /u/filosoful:

Taiwan Semiconductor Manufacturing Co. (TSMC), the world's largest contract chipmaker, touted its 3 nanometer process as the world's most advanced semiconductor technology on Thursday at a ceremony announcing the start of mass production of chips using the highly anticipated technology.

The 3nm process yield rate is comparable to that of the 5nm technology and demand for 3nm chips is very strong, said TSMC Chairman Mark Liu (劉德音) during the ceremony held at TSMC's Fab 18 in the Southern Taiwan Science Park in Tainan.

Liu said TSMC's 3nm technology would feature an estimated 60 percent gain in density of logic transistors and reduce power consumption by 30 percent to 35 percent at the same rate compared with 5nm technology.

Higher logic density means smaller transistors that operate faster and require less power to operate can be produced.

Please reply to OP's comment here: https://old.reddit.com/r/Futurology/comments/zyfny7/tsmc_starts_volume_production_of_3nm_chips/j25jnm7/

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TerpenesByMS t1_j29rgt5 wrote

Jesus that's twenty carbon-carbon bonds.

Is this actually real or is "3 nm" cooking the books with a technicality somehow?

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MugSoft t1_j29vwre wrote

“3 nm” is just a marketing name, not actually connected to the size of the transistor.

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